IRS2500SPBF【PDF 14/22 页】IC PFC

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Sheet目录38

10页 11页 12页 13页 [14页]15页 16页 17页 18页

IRS2500S

www.irf.com

?2012 International Rectifier

LPFC

OUT

VOCTH

. . .

Figure 12: Inductor current, OUT pin, ZX pin and

OC pin timing diagram.

On-time Modulation Circuit

A fixed on-time of MPFC over an entire cycle of the

line input voltage produces a peak inductor current

which naturally follows the sinusoidal shape of the

line input voltage. The smoothed, averaged line

input current is in phase with the line input voltage

for high power factor but a high total harmonic

distortion (THD), as well as individual higher

harmonics, of the current are still possible. This is

mostly due to cross-over distortion of the line

current near the zero-crossings of the line input

voltage. To achieve low harmonics that are

acceptable for compliance with international

standards and general market requirements, an

additional on-time modulation circuit has been

added to the PFC control. This circuit dynamically

increases the on-time of MPFC as the line input

voltage nears the zero-crossings (Figure 13). This

causes the peak LPFC current, and therefore the

smoothed line input current, to increase near the

zero-crossings of the line input voltage. This

reduces the amount of cross-over distortion in the

line input current which reduces the THD and

higher harmonics. The on time modulation function

is controlled via the VDC input. The full wave

rectified voltage from the bridge rectifier is divided

down by RIN and RDC to provide an input with a

peak voltage of approximately 1V at 90VAC input

and 3V at 277VAC. CDC is added to remove noise

from the signal, the value is typically 10nF. The on

time modulation function is not required in some

applications. In such cases the VDC input should

be tied to VCC through a 10K resistor.

LPFC

OUT

near peak region of

rectified AC line

near zero-crossing region

of rectified AC line

Figure 13: On-time modulation circuit timing

diagram.

Output Over-voltage Protection

The IRS2500 incorporates both static and dynamic

overvoltage protection. Static over voltage

protection monitors the feedback voltage at the

VBUS pin and disables the gate drive output if this

voltage exceeds the target voltage by 8%. This is

activated by an internal comparator set to detect a

threshold of 2.7V, which is 8% above the regulation

threshold of 2.5V.

However, under startup condition or when a load is

removed from the output the error amplifier output

voltage at the COMP pin swings low. Since the

compensation capacitor CCOMP is connected from

this output back to the VBUS input a current will

flow during the COMP voltage transition. This pulls

down the VBUS voltage, which allows the output

voltage to exceed the desired regulation level

during the transition and results in an overshoot

before the voltage at the VBUS input exceeds the

regulation threshold.

In order to compensate for this effect, the IRS2500

includes dynamic detection of the error amplifier

output current. During a swing in the negative

direction the error amplifier output current peaks at

a much high level than the level during steady state

operation. This higher current is internally detected

and triggers the overvoltage protection circuitry

disabling the PWM output until the error amplifier

output has settled to a new level. This prevents the

output voltage from overshooting the desired level

by a significant amount under the transient

conditions described. For this reason the loop

should be designed such that voltage ripple at

COMP is minimized during steady state operation.

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